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• (sleep average - * calculation, priority modifiers, etc. ... (sleep average + * calculation, priority modifiers, etc. ... We update - * an 'average sleep time' value here, based on - * ->last_run. ... + * + * The boost works by updating the 'average sleep time' + * value here, based on ->last_run. ... */ - if (unlikely(sync && !task_running(rq, p) && + if (unlikely(sync && !task_running(p) && (task_cpu(p) != smp_processor_id()) && (p->cpus_allowed & (1UL prio curr->prio) - resched_task(rq->curr); + requeue_waker = activate_task(p, rq); + wake_up_cpu(rq, task_cpu(p), p); } success = 1; } #if CONFIG_SMP else - if (unlikely(kick) && task_running(rq, p) && + if (unlikely(kick) && task_running(p) && (p->cpu != smp_processor_id())) smp_send_reschedule(p->cpu); #endif - if (p->state >= TASK_ZOMBIE) - BUG(); p->state = TASK_RUNNING; } task_rq_unlock(rq, &flags); + /* + * We have to do this outside the other spinlock, the two + * runqueues might be different: + */ + if (requeue_waker) { + prio_array_t *array; + + rq = task_rq_lock(current, &flags); + array = current->array; + dequeue_task(current, array); + current->prio = effective_prio(current); + enqueue_task(current, array); + task_rq_unlock(rq, &flags); + } + return success; } @@ -462,30 +650,25 @@ void wake_up_forked_process(task_t * p) runqueue_t *rq = task_rq_lock(current, &flags); p->state = TASK_RUNNING; - if (!rt_task(p)) { - /* - * We decrease the sleep average of forking parents - * and children as well, to keep max-interactive tasks - * from forking tasks that are max-interactive. - */ - current->sleep_avg = current->sleep_avg * PARENT_PENALTY / 100; - p->sleep_avg = p->sleep_avg * CHILD_PENALTY / 100; - p->prio = effective_prio(p); - } + /* + * We decrease the sleep average of forking parents + * and children as well, to keep max-interactive tasks + * from forking tasks that are max-interactive. ... + * This is accomplished by forcing the cpu_allowed mask to only + * allow dest_cpu, which will force the cpu onto dest_cpu. Then + * the cpu_allowed mask is restored. ... per_cpu_system cpu += sys_ticks; /* Task might have expired already, but not scheduled off yet */ + spin_lock(&rq->lock); if (p->array != rq->active) { set_tsk_need_resched(p); + spin_unlock(&rq->lock); return; } - spin_lock(&rq->lock); + /* + * The task was running during this tick - update the + * time slice counter and the sleep average. Note: we + * do not update a thread's priority until it either + * goes to sleep or uses up its timeslice. ... @@ -943,16 +1442,6 @@ void scheduler_tick(int user_ticks, int } goto out; } - /* - * The task was running during this tick - update the - * time slice counter and the sleep average.

• The Shadow, Dime Mystery Detective, The Black Mask zählen hier zu den Bekanntesten, zwei der Black-Mask-Autoren, Dashiell Hammett und Raymond Chandler lieferten auch die Vorlagen zu den bekanntesten Films noirs, Die Spur des Falken (Originaltitel: The Maltese Falcon) und Tote schlafen fest (The Big Sleep). ...

• While you sleep. ...
• The NovaDreamer detects when you are dreaming by sensing the movements of your eyes during REM sleep with photoelectric sensors. The sensors are mounted in asleep mask worn over your eyes (nothing touches your eyelids). ...
• The cue to become lucid is a light or a sound from the mask, in a variety of patterns, according to your choice. ...
• REM-detection: Advanced microtechnology enables full REM-sensing ability inside of a light, comfortable mask .
• Compact and comfortable: MI the electronics are in the soft, flexible sleep mask. ...

• 1 I'm Single, I sleep with a machine at night. ... Will a humidification device wear out my mask and machine?         11. ... How do I know what mask is best for me?                                        15. ... What is a Polysomnogragh or Sleep Test?.
• I'm single, I sleep with a machine at night. ...
•   It is not your fault you have sleep apnea. ... So, explain to your date that you have sleep apnea, and you use a machine to help control your snoring. ...
• Place your CPAP mask on your face and turn the machine on. ...
• Some people keep a Tic-Tac mint next to their bed, they put a mint in their cheeks, and go back to sleep.
• There is no cure for Obstructive Sleep Apnea (OSA). ...  Having to wear a little mask every night is a small price to pay for restored sleep and more energy during the day. ...
• Some machines come with compliance monitors that determine if you are getting enough sound sleep. ...
• Instead of using a face or nose mask, many people choose nasal pillows or adam circuits. ...
• Generally, you should clean your mask daily, some manufacturers recommend you soak mask in soapy water for 10-minutes, rinse and air dry. ...
• Will a humidification device wear out my mask and machine?.
• How do I know what mask is best for me?.

• He taught himself to write pulp fiction in an effort to draw an income from his talent, and his first story was published in Black Mask in 1933. His first novel, The Big Sleep, was published in 1939. ...
• The Big Sleep (1939), his first .
• Farewell, My Lovely, The Big Sleep and The Long Goodbye are arguably his masterpieces. ...

• 1933 erschien die erste Kurzgeschichte Chandlers ("Blackmailers Don’t Shot") im Journal Black Mask. ... Der erste Roman "The Big sleep" erschien 1939 und wird ein großer Erfolg. ...
• "The big Sleep" (1939) (dt. ...
• 1946 The Big Sleep (Regie: Howard Hawks) nach: The Big Sleep .
• 1978 The Big Sleep (Regie: Michael Winner) nach: The Big Sleep .

• Silk Sleep Mask  .
• Generously stuffed with soft cotton batting, the Silk Sleep Mask prevents light from coming through so you experience a deeper, more rejuvenating sleep. ...
• Silk Sleep Mask.
• Health Solutions for Sleep Kits with FREE DVD.

•   Sleep-Mask by Magna-Pak-FM1 #271.
• The Sleep-Mask is an all north pole magnetic face mask. ...
• The Sleep-Mask is an all north pole magnetic face mask. ...

• Talk About Sleep Message Boards » Snoring & Sleep Apnea » Assorted CPAP problems. ...
• 1) Mask leaks - I don't know if they are enough to lessen the effect of the air pressure, but they are darn annoying. ... Tightening the mask has caused red sores on my face. ...
• As for the mask, what type do you have? If you look on this site you'll see lots of opinions about masks, and everyone has a favorite. ...
• >Tightening the mask has caused red sores on my face.
• A small price to pay, but it seems you need a better fitting mask.
• Mask leakage: the bane of most every new hosehead. ... To make sure you've done everything possible before moving on to a new mask, also make sure you wash you face and mask every night with a mild soap. ...
• Read through old posts here and maybe you can try the favorite mask of someone whose problems with gear you identify with. Most insurance plans will buy you a new mask every few-6-12 months. ...
• Maybe I will try loosening the mask a little to relieve the air leaks, this seems to be popular opinion. ...
• As far as the mouth open thing goes, I thought that the full mask was designed for people with open mouth sleep. When I went in for my CPAP test at the clinic, I tried the nostril mask first, and everything was fine until the doctor came into the room and told me I had to use the full mask because my mouth naturally opens when I fall asleep. There is nothing I can do about that, and I know I am not alone, so certainly the full mask is the solution? .
• I don't know which mask you have, but many masks have an angle adjustment on the forehead pads. ...
• com It is curved to prevent the pillow from interfering with the mask seal, by letting the mask suspend over the edge.

• Sleep Mask w/ Rhinestones.
• Mary Green's silk sleep masks are made of 100% silk for comfort. ...
• This silk sleep mask is decorated with adorable rhinestone sayings. ...
• just slip on your Mary green sleep mask and dream away! .

• + #define DEBUG 0 @@ -87,21 +168,105 @@ #define RTRACE if(0) printk #endif +enum radeon_chips { + RADEON_QD, + RADEON_QE, + RADEON_QF, + RADEON_QG, + RADEON_QY, + RADEON_QZ, + RADEON_LW, + RADEON_LX, + RADEON_LY, + RADEON_LZ, + RADEON_QL, + RADEON_QN, + RADEON_QO, + RADEON_Ql, + RADEON_BB, + RADEON_QM, + RADEON_QW, + RADEON_QX, + RADEON_Id, + RADEON_Ie, + RADEON_If, + RADEON_Ig, + RADEON_Y_, + RADEON_Ld, + RADEON_Le, + RADEON_Lf, + RADEON_Lg, + RADEON_LR, + RADEON_ND, + RADEON_NE, + RADEON_AE, + RADEON_AF, + RADEON_AD, + RADEON_NH, + RADEON_NI, + RADEON_AP, + RADEON_AR, + RADEON_NF, +}; +enum radeon_arch { + RADEON_PM, + RADEON_R100, + RADEON_M6, + RADEON_RV100, + RADEON_R200, + RADEON_M7, + RADEON_RV200, + RADEON_M9, + RADEON_RV250, + RADEON_RV280, + RADEON_R300, + RADEON_R350, + RADEON_RV350, +}; -enum radeon_chips { - RADEON_QD, /* Radeon R100 */ - RADEON_QE, /* Radeon R100 */ - RADEON_QF, /* Radeon R100 */ - RADEON_QG, /* Radeon R100 */ - RADEON_QY, /* Radeon RV100 (VE) */ - RADEON_QZ, /* Radeon RV100 (VE) */ - RADEON_QL, /* Radeon R200 (8500) */ - RADEON_QW, /* Radeon RV200 (7500) */ - RADEON_LW, /* Radeon Mobility M7 */ - RADEON_LY, /* Radeon Mobility M6 */ - RADEON_LZ, /* Radeon Mobility M6 */ - RADEON_PM /* Radeon Mobility P/M */ +static struct radeon_chip_info { + const char *name; + unsigned char arch; +} radeon_chip_info __devinitdata = { + { "QD", RADEON_R100 }, + { "QE", RADEON_R100 }, + { "QF", RADEON_R100 }, + { "QG", RADEON_R100 }, + { "VE QY", RADEON_RV100 }, + { "VE QZ", RADEON_RV100 }, + { "M7 LW", RADEON_M7 }, + { "M7 LX", RADEON_M7 }, + { "M6 LY", RADEON_M6 }, + { "M6 LZ", RADEON_M6 }, + { "8500 QL", RADEON_R200 }, + { "8500 QN", RADEON_R200 }, + { "8500 QO", RADEON_R200 }, + { "8500 Ql", RADEON_R200 }, + { "8500 BB", RADEON_R200 }, + { "9100 QM", RADEON_R200 }, + { "7500 QW", RADEON_RV200 }, + { "7500 QX", RADEON_RV200 }, + { "9000 Id", RADEON_RV250 }, + { "9000 Ie", RADEON_RV250 }, + { "9000 If", RADEON_RV250 }, + { "9000 Ig", RADEON_RV250 }, + { "9200 Y", RADEON_RV280 }, + { "M9 Ld", RADEON_M9 }, + { "M9 Le", RADEON_M9 }, + { "M9 Lf", RADEON_M9 }, + { "M9 Lg", RADEON_M9 }, + { "PM LR", RADEON_PM }, + { "9700 ND", RADEON_R300 }, + { "9700 NE", RADEON_R300 }, + { "9700 AE", RADEON_R300 }, + { "9700 AF", RADEON_R300 }, + { "9500 AD", RADEON_R300 }, + { "9800 NH", RADEON_R350 }, + { "9800 NI", RADEON_R350 }, + { "9600 AP", RADEON_RV350 }, + { "9600 AR", RADEON_RV350 }, + { "9600 NF", RADEON_RV350 }, }; @@ -117,18 +282,44 @@ static struct pci_device_id radeonfb_pci_table __devinitdata = { - { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QD}, - { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QE}, - { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QF}, - { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QG, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QG}, - { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QY}, - { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QZ}, - { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QL, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QL}, - { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QW}, - { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LW}, - { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LY}, - { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LZ}, - { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_PM, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_PM}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QD}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QE}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QF}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QG, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QG}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QY}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QZ}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LW}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LX}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LY}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LZ}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QL, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QL}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QN, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QN}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QO, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QO}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ql, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ql}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_BB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_BB}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QM, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QM}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QW}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QX}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Id}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ie, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ie}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_If, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_If}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ig, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ig}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ld, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ld}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Le, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Le}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Lf, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Lf}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Lg, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Lg}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LR, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LR}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_ND, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_ND}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_NE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_NE}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_AE}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_AF}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_NH, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_NH}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_NI, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_NI}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Y_, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Y_}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_AD}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_AP, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_AP}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_AR, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_AR}, + { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_NF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_NF}, { 0, } }; MODULE_DEVICE_TABLE(pci, radeonfb_pci_table); @@ -155,7 +346,15 @@ { CAP0_TRIG_CNTL, 0 }, }; -#define COMMON_REGS_SIZE = (sizeof(common_regs)/sizeof(common_regs 0 )) +reg_val common_regs_m6 = { + { OVR_CLR, 0 }, + { OVR_WID_LEFT_RIGHT, 0 }, + { OVR_WID_TOP_BOTTOM, 0 }, + { OV0_SCALE_CNTL, 0 }, + { SUBPIC_CNTL, 0 }, + { GEN_INT_CNTL, 0 }, + { CAP0_TRIG_CNTL, 0 } +}; typedef struct { u8 clock_chip_type; @@ -215,7 +414,8 @@ u32 crtc_gen_cntl; u32 crtc_ext_cntl; u32 dac_cntl; - + u32 crtc_more_cntl; + u32 flags; u32 pix_clock; int xres, yres; @@ -227,7 +427,8 @@ /* PLL regs */ u32 ppll_div_3; u32 ppll_ref_div; - + u32 vclk_ecp_cntl; + /* Flat panel regs */ u32 fp_crtc_h_total_disp; u32 fp_crtc_v_total_disp; @@ -242,27 +443,28 @@ u32 tmds_crc; u32 tmds_transmitter_cntl; -#if defined(__BIG_ENDIAN) + u32 display_base_addr; + u32 mc_fb_location; u32 surface_cntl; -#endif }; struct radeonfb_info { struct fb_info info; - struct radeon_regs state; struct radeon_regs init_state; - char name 17 ; + char name 32 ; char ram_type 12 ; - u32 mmio_base_phys; - u32 fb_base_phys; + unsigned long mmio_base_phys; + unsigned long fb_base_phys; unsigned long mmio_base; unsigned long fb_base; + u32 fb_local_base; + struct pci_dev *pdev; unsigned char *EDID; @@ -275,15 +477,18 @@ struct { u8 red, green, blue, pad; } palette 256 ; int chipset; + unsigned char arch; int video_ram; u8 rev; int pitch, bpp, depth; int xres, yres, pixclock; + int xres_virtual, yres_virtual; - int use_default_var; - int got_dfpinfo; - - int hasCRTC2; + char use_default_var; + char got_dfpinfo; + char hasCRTC2; + char accel_enabled; + int crtDisp_type; int dviDisp_type; @@ -301,8 +506,7 @@ struct ram_info ram; - u32 hack_crtc_ext_cntl; - u32 hack_crtc_v_sync_strt_wid; + int mtrr_hdl; #if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB32) union { @@ -319,10 +523,12 @@ #endif #ifdef CONFIG_PMAC_PBOOK - unsigned char *save_framebuffer; int pm_reg; + u32 save_regs 64 ; + u32 mdll, mdll2; #endif - + int asleep; + struct radeonfb_info *next; }; @@ -344,8 +550,12 @@ #define INREG(addr) readl((rinfo->mmio_base)+addr) #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr) -#define OUTPLL(addr,val) OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000001f) | 0x00000080); \ - OUTREG(CLOCK_CNTL_DATA, val) +#define OUTPLL(addr,val) \ + do { \ + OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000003f) | 0x00000080); \ + OUTREG(CLOCK_CNTL_DATA, val); \ + } while(0) + #define OUTPLLP(addr,val,mask) \ do { \ unsigned int _tmp = INPLL(addr); \ @@ -363,9 +573,9 @@ } while (0) -static __inline__ u32 _INPLL(struct radeonfb_info *rinfo, unsigned long addr) +static __inline__ u32 _INPLL(struct radeonfb_info *rinfo, u32 addr) { - OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000001f); + OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f); return (INREG(CLOCK_CNTL_DATA)); } @@ -424,7 +634,7 @@ } -static __inline__ void _radeon_fifo_wait (struct radeonfb_info *rinfo, int entries) +static __inline__ void radeon_fifo_wait (struct radeonfb_info *rinfo, int entries) { int i; @@ -434,12 +644,12 @@ } -static __inline__ void _radeon_engine_idle (struct radeonfb_info *rinfo) +static __inline__ void radeon_engine_idle (struct radeonfb_info *rinfo) { int i; /* ensure FIFO is empty before waiting for idle */ - _radeon_fifo_wait (rinfo, 64); + radeon_fifo_wait(rinfo, 64); for (i=0; i= val2) @@ -596,15 +777,27 @@ static char fontname 40 __initdata; static char *mode_option __initdata; -static char noaccel __initdata = 0; +static char noaccel = 0; +static char mirror = 0; static int panel_yres __initdata = 0; static char force_dfp __initdata = 0; +static char force_crt __initdata = 0; +static char force_nolcd __initdata = 0; static struct radeonfb_info *board_list = NULL; +static char nomtrr __initdata = 0; #ifdef FBCON_HAS_CFB8 static struct display_switch fbcon_radeon8; #endif +#ifdef FBCON_HAS_CFB16 +static struct display_switch fbcon_radeon16; +#endif + +#ifdef FBCON_HAS_CFB32 +static struct display_switch fbcon_radeon32; +#endif + /* * prototypes @@ -636,7 +829,7 @@ static void radeon_set_dispsw (struct radeonfb_info *rinfo, struct display *disp); static void radeon_save_state (struct radeonfb_info *rinfo, struct radeon_regs *save); -static void radeon_engine_init (struct radeonfb_info *rinfo); +static int radeon_engine_init (struct radeonfb_info *rinfo); static void radeon_load_video_mode (struct radeonfb_info *rinfo, struct fb_var_screeninfo *mode); static void radeon_write_mode (struct radeonfb_info *rinfo, @@ -647,35 +840,33 @@ static int radeonfb_pci_register (struct pci_dev *pdev, const struct pci_device_id *ent); static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev); -static char *radeon_find_rom(struct radeonfb_info *rinfo); -static void radeon_get_pllinfo(struct radeonfb_info *rinfo, char *bios_seg); -static void radeon_get_moninfo (struct radeonfb_info *rinfo); -static int radeon_get_dfpinfo (struct radeonfb_info *rinfo); -static int radeon_get_dfpinfo_BIOS(struct radeonfb_info *rinfo); -static void radeon_get_EDID(struct radeonfb_info *rinfo); -static int radeon_dfp_parse_EDID(struct radeonfb_info *rinfo); -static void radeon_update_default_var(struct radeonfb_info *rinfo); - - -#ifdef CONFIG_ALL_PPC -static int radeon_read_OF (struct radeonfb_info *rinfo); -static int radeon_get_EDID_OF(struct radeonfb_info *rinfo); -extern struct device_node *pci_device_to_OF_node(struct pci_dev *dev); #ifdef CONFIG_PMAC_PBOOK -int radeon_sleep_notify(struct pmu_sleep_notifier *self, int when); +static int radeon_sleep_notify(struct pmu_sleep_notifier *self, int when); static struct pmu_sleep_notifier radeon_sleep_notifier = { radeon_sleep_notify, SLEEP_LEVEL_VIDEO, }; +#endif /* CONFIG_PMAC_PBOOK */ +#ifdef CONFIG_PMAC_BACKLIGHT static int radeon_set_backlight_enable(int on, int level, void *data); static int radeon_set_backlight_level(int level, void *data); static struct backlight_controller radeon_backlight_controller = { radeon_set_backlight_enable, radeon_set_backlight_level }; -#endif /* CONFIG_PMAC_PBOOK */ +#endif /* CONFIG_PMAC_BACKLIGHT */ + + +static void OUTMC( struct radeonfb_info *rinfo, u8 indx, u32 value); +static u32 INMC(struct radeonfb_info *rinfo, u8 indx); +static void radeon_pm_disable_dynamic_mode(struct radeonfb_info *rinfo); +static void radeon_pm_enable_dynamic_mode(struct radeonfb_info *rinfo); +static void radeon_pm_yclk_mclk_sync(struct radeonfb_info *rinfo); +static void radeon_pm_program_mode_reg(struct radeonfb_info *rinfo, u16 value, u8 delay_required); +static void radeon_pm_enable_dll(struct radeonfb_info *rinfo); +static void radeon_pm_full_reset_sdram(struct radeonfb_info *rinfo); + -#endif /* CONFIG_ALL_PPC */ static struct fb_ops radeon_fb_ops = { fb_get_fix: radeonfb_get_fix, @@ -729,10 +920,20 @@ memcpy(fontname, this_opt + 5, i); } else if (!strncmp(this_opt, "noaccel", 7)) { noaccel = 1; + } else if (!strncmp(this_opt, "mirror", 6)) { + mirror = 1; } else if (!strncmp(this_opt, "dfp", 3)) { force_dfp = 1; + force_nolcd = 1; + } else if (!strncmp(this_opt, "crt", 3)) { + force_crt = 1; + force_nolcd = 1; + } else if (!strncmp(this_opt, "nolcd", 5)) { + force_nolcd = 1; } else if (!strncmp(this_opt, "panel_yres:", 11)) { panel_yres = simple_strtoul((this_opt+11), NULL, 0); + } else if (!strncmp(this_opt, "nomtrr", 6)) { + nomtrr = 1; } else mode_option = this_opt; } @@ -750,835 +951,996 @@ MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset"); MODULE_LICENSE("GPL"); -static int radeonfb_pci_register (struct pci_dev *pdev, - const struct pci_device_id *ent) +MODULE_PARM(noaccel, "i"); +MODULE_PARM_DESC(noaccel, "Disable (1) or enable (0) the usage of the 2d-accelerator"); +MODULE_PARM(force_dfp, "i"); +MODULE_PARM_DESC(force_dfp,"Force (1) the usage of a digital flat panel"); +MODULE_PARM(force_crt, "i"); +MODULE_PARM_DESC(force_crt,"Force (1) the usage of a CRT monitor"); +MODULE_PARM(force_nolcd, "i"); +MODULE_PARM_DESC(force_nolcd,"Avoid (1) the usage of a digital flat panel"); + +static unsigned char *radeon_find_rom(struct radeonfb_info *rinfo) +{ +#if defined(__i386__) + /* I simplified this code as we used to miss the signatures in + * a lot of case. ... xclk); } +} - /* framebuffer size */ - tmp = INREG(CONFIG_MEMSIZE); - /* mem size is bits 28:0 , mask off the rest */ - rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK; +static void radeon_get_moninfo (struct radeonfb_info *rinfo) +{ + unsigned int tmp; - /* According to XFree86 4. ... + */ + + return 1; } + + return 1; } -static void radeon_get_moninfo (struct radeonfb_info *rinfo) +static int radeonfb_pci_register (struct pci_dev *pdev, + const struct pci_device_id *ent) { - unsigned int tmp; + struct radeonfb_info *rinfo; + struct radeon_chip_info *rci = &radeon_chip_info ent->driver_data ; + u32 tmp; + int i, j; - if (force_dfp) { - rinfo->dviDisp_type = MT_DFP; - return; + RTRACE("radeonfb_pci_register BEGIN\n"); + + rinfo = kmalloc (sizeof (struct radeonfb_info), GFP_KERNEL); + if (!rinfo) { + printk ("radeonfb: could not allocate memory\n"); + return -ENODEV; } - tmp = INREG(RADEON_BIOS_4_SCRATCH); + memset (rinfo, 0, sizeof (struct radeonfb_info)); - if (rinfo->hasCRTC2) { - /* primary DVI port */ - if (tmp & 0x08) - rinfo->dviDisp_type = MT_DFP; - else if (tmp & 0x4) - rinfo->dviDisp_type = MT_LCD; - else if (tmp & 0x200) - rinfo->dviDisp_type = MT_CRT; - else if (tmp & 0x10) - rinfo->dviDisp_type = MT_CTV; - else if (tmp & 0x20) - rinfo->dviDisp_type = MT_STV; + rinfo->pdev = pdev; + strcpy(rinfo->name, rci->name); + rinfo->arch = rci->arch; - /* secondary CRT port */ - if (tmp & 0x2) - rinfo->crtDisp_type = MT_CRT; - else if (tmp & 0x800) - rinfo->crtDisp_type = MT_DFP; - else if (tmp & 0x400) - rinfo->crtDisp_type = MT_LCD; - else if (tmp & 0x1000) - rinfo->crtDisp_type = MT_CTV; - else if (tmp & 0x2000) - rinfo->crtDisp_type = MT_STV; - } else { - rinfo->dviDisp_type = MT_NONE; - - tmp = INREG(FP_GEN_CNTL); + /* enable device */ + { + int err; - if (tmp & FP_EN_TMDS) - rinfo->crtDisp_type = MT_DFP; - else - rinfo->crtDisp_type = MT_CRT; + if ((err = pci_enable_device(pdev))) { + printk("radeonfb: cannot enable device\n"); + kfree (rinfo); + return -ENODEV; + } } -} + /* set base addrs */ + rinfo->fb_base_phys = pci_resource_start (pdev, 0); + rinfo->mmio_base_phys = pci_resource_start (pdev, 2); + /* request the mem regions */ + if (!request_mem_region (rinfo->fb_base_phys, + pci_resource_len(pdev, 0), "radeonfb")) { + printk ("radeonfb: cannot reserve FB region\n"); + kfree (rinfo); + return -ENODEV; + } -static void radeon_get_EDID(struct radeonfb_info *rinfo) -{ -#ifdef CONFIG_ALL_PPC - if (!radeon_get_EDID_OF(rinfo)) - RTRACE("radeonfb: could not retrieve EDID from OF\n"); -#else - /* XXX use other methods later */ -#endif -} + if (!request_mem_region (rinfo->mmio_base_phys, + pci_resource_len(pdev, 2), "radeonfb")) { + printk ("radeonfb: cannot reserve MMIO region\n"); + release_mem_region (rinfo->fb_base_phys, + pci_resource_len(pdev, 0)); + kfree (rinfo); + return -ENODEV; + } + /* map the regions */ + rinfo->mmio_base = (u32) ioremap (rinfo->mmio_base_phys, + RADEON_REGSIZE); + if (!rinfo->mmio_base) { + printk ("radeonfb: cannot map MMIO\n"); + release_mem_region (rinfo->mmio_base_phys, + pci_resource_len(pdev, 2)); + release_mem_region (rinfo->fb_base_phys, + pci_resource_len(pdev, 0)); + kfree (rinfo); + return -ENODEV; + } -#ifdef CONFIG_ALL_PPC -static int radeon_get_EDID_OF(struct radeonfb_info *rinfo) -{ - struct device_node *dp; - unsigned char *pedid = NULL; + rinfo->chipset = pdev->device; - dp = pci_device_to_OF_node(rinfo->pdev); - pedid = (unsigned char *) get_property(dp, "DFP,EDID", 0); - if (!pedid) - pedid = (unsigned char *) get_property(dp, "LCD,EDID", 0); - if (!pedid) - pedid = (unsigned char *) get_property(dp, "EDID", 0); + switch (rinfo->arch) { + case RADEON_R100: + rinfo->hasCRTC2 = 0; + break; + default: + /* all the rest have it */ + rinfo->hasCRTC2 = 1; + break; + } + if (mirror) + printk("radeonfb: mirroring display to CRT\n"); - if (pedid) { - rinfo->EDID = pedid; - return 1; - } else - return 0; -} -#endif /* CONFIG_ALL_PPC */ + /* framebuffer size */ + tmp = INREG(CONFIG_MEMSIZE); + /* mem size is bits 28:0 , mask off the rest */ + rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK; -static int radeon_dfp_parse_EDID(struct radeonfb_info *rinfo) -{ - unsigned char *block = rinfo->EDID; + /* ram type */ + tmp = INREG(MEM_SDRAM_MODE_REG); + switch ((MEM_CFG_TYPE & tmp) >> 30) { + case 0: + /* SDR SGRAM (2:1) */ + strcpy(rinfo->ram_type, "SDR SGRAM"); + rinfo->ram. ... blue = default_blu j ; } - if (!(tmp = rinfo->bios_seg + readw(fpbiosstart + 0x40))) { - printk("radeonfb: Failed to detect DFP panel info using BIOS\n"); - return 0; - } - - for(i=0; ipanel_xres = readw(tmp + 25); - rinfo->panel_yres = readw(tmp + 27); - printk("radeonfb: detected DFP panel size from BIOS: %dx%d\n", - rinfo->panel_xres, rinfo->panel_yres); - - for(i=0; ibios_seg + readw(tmp+64+i*2); - if (tmp0 == 0) - break; - if ((readw(tmp0) == rinfo->panel_xres) && - (readw(tmp0+2) == rinfo->panel_yres)) { - rinfo->hblank = (readw(tmp0+17) - readw(tmp0+19)) * 8; - rinfo->hOver_plus = ((readw(tmp0+21) - readw(tmp0+19) -1) * 8) & 0x7fff; - rinfo->hSync_width = readb(tmp0+23) * 8; - rinfo->vblank = readw(tmp0+24) - readw(tmp0+26); - rinfo->vOver_plus = (readw(tmp0+28) & 0x7ff) - readw(tmp0+26); - rinfo->vSync_width = (readw(tmp0+28) & 0xf800) >> 11; - rinfo->clock = readw(tmp0+9); + pci_set_drvdata(pdev, rinfo); + rinfo->next = board_list; + board_list = rinfo; - rinfo->got_dfpinfo = 1; - return 1; - } + if (register_framebuffer ((struct fb_info *) rinfo) fb_base); + iounmap ((void*)rinfo->mmio_base); + release_mem_region (rinfo->mmio_base_phys, + pci_resource_len(pdev, 2)); + release_mem_region (rinfo->fb_base_phys, + pci_resource_len(pdev, 0)); + kfree (rinfo); + return -ENODEV; } - return 0; -} - - - -static int radeon_get_dfpinfo (struct radeonfb_info *rinfo) -{ - unsigned int tmp; - unsigned short a, b; - - if (radeon_get_dfpinfo_BIOS(rinfo)) - radeon_update_default_var(rinfo); - - if (radeon_dfp_parse_EDID(rinfo)) - radeon_update_default_var(rinfo); - - if (!rinfo->got_dfpinfo) { - /* - * it seems all else has failed now and we - * resort to probing registers for our DFP info - */ - if (panel_yres) { - rinfo->panel_yres = panel_yres; - } else { - tmp = INREG(FP_VERT_STRETCH); - tmp &= 0x00fff000; - rinfo->panel_yres = (unsigned short)(tmp >> 0x0c) + 1; - } - - switch (rinfo->panel_yres) { - case 480: - rinfo->panel_xres = 640; - break; - case 600: - rinfo->panel_xres = 800; - break; - case 768: -#if defined(__powerpc__) - if (rinfo->dviDisp_type == MT_LCD) - rinfo->panel_xres = 1152; - else +#ifdef CONFIG_MTRR + rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys, + rinfo->video_ram, + MTRR_TYPE_WRCOMB, 1); #endif - rinfo->panel_xres = 1024; - break; - case 1024: - rinfo->panel_xres = 1280; - break; - case 1050: - rinfo->panel_xres = 1400; - break; - case 1200: - rinfo->panel_xres = 1600; - break; - default: - printk("radeonfb: Failed to detect DFP panel size\n"); - return 0; - } - - printk("radeonfb: detected DFP panel size from registers: %dx%d\n", - rinfo->panel_xres, rinfo->panel_yres); - - tmp = INREG(FP_CRTC_H_TOTAL_DISP); - a = (tmp & FP_CRTC_H_TOTAL_MASK) + 4; - b = (tmp & 0x01ff0000) >> FP_CRTC_H_DISP_SHIFT; - rinfo->hblank = (a - b + 1) * 8; - tmp = INREG(FP_H_SYNC_STRT_WID); - rinfo->hOver_plus = (unsigned short) ((tmp & FP_H_SYNC_STRT_CHAR_MASK) >> - FP_H_SYNC_STRT_CHAR_SHIFT) - b - 1; - rinfo->hOver_plus *= 8; - rinfo->hSync_width = (unsigned short) ((tmp & FP_H_SYNC_WID_MASK) >> - FP_H_SYNC_WID_SHIFT); - rinfo->hSync_width *= 8; - tmp = INREG(FP_CRTC_V_TOTAL_DISP); - a = (tmp & FP_CRTC_V_TOTAL_MASK) + 1; - b = (tmp & FP_CRTC_V_DISP_MASK) >> FP_CRTC_V_DISP_SHIFT; - rinfo->vblank = a - b /* + 24 */ ; +#ifdef CONFIG_PMAC_BACKLIGHT + if (rinfo->dviDisp_type == MT_LCD) + register_backlight_controller(&radeon_backlight_controller, + rinfo, "ati"); +#endif - tmp = INREG(FP_V_SYNC_STRT_WID); - rinfo->vOver_plus = (unsigned short) (tmp & FP_V_SYNC_STRT_MASK) - - b + 1; - rinfo->vSync_width = (unsigned short) ((tmp & FP_V_SYNC_WID_MASK) >> - FP_V_SYNC_WID_SHIFT); + printk ("radeonfb: ATI Radeon %s %s %d MB\n", rinfo->name, rinfo->ram_type, + (rinfo->video_ram/(1024*1024))); - return 1; + if (rinfo->hasCRTC2) { + printk("radeonfb: DVI port %s monitor connected\n", + GET_MON_NAME(rinfo->dviDisp_type)); + printk("radeonfb: CRT port %s monitor connected\n", + GET_MON_NAME(rinfo->crtDisp_type)); + } else { + printk("radeonfb: CRT port %s monitor connected\n", + GET_MON_NAME(rinfo->crtDisp_type)); } - return 1; -} +#ifdef CONFIG_PMAC_PBOOK + if (rinfo->arch == RADEON_M6 || rinfo->arch == RADEON_M7 || rinfo->arch == RADEON_M9) { + /* Find PM registers in config space */ + rinfo->pm_reg = pci_find_capability(pdev, PCI_CAP_ID_PM); + /* Enable dynamic PM of chip clocks */ + radeon_pm_enable_dynamic_mode(rinfo); + /* Register sleep callbacks */ + pmu_register_sleep_notifier(&radeon_sleep_notifier); + printk("radeonfb: Power Management enabled for Mobility chipsets\n"); + } +#endif + RTRACE("radeonfb_pci_register END\n"); -#ifdef CONFIG_ALL_PPC -static int radeon_read_OF (struct radeonfb_info *rinfo) -{ - struct device_node *dp; - unsigned int *xtal; + return 0; +} - dp = pci_device_to_OF_node(rinfo->pdev); - xtal = (unsigned int *) get_property(dp, "ATY,RefCLK", 0); - rinfo->pll. ref_clk = *xtal / 10; +static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev) +{ + struct radeonfb_info *rinfo = pci_get_drvdata(pdev); + + if (!rinfo) + return; + + /* restore original state */ + radeon_write_mode (rinfo, &rinfo->init_state); + +#ifdef CONFIG_MTRR + if (rinfo->mtrr_hdl >= 0) + mtrr_del(rinfo->mtrr_hdl, 0, 0); +#endif - if (*xtal) - return 1; - else - return 0; + unregister_framebuffer ((struct fb_info *) rinfo); + + iounmap ((void*)rinfo->mmio_base); + iounmap ((void*)rinfo->fb_base); + + release_mem_region (rinfo->mmio_base_phys, + pci_resource_len(pdev, 2)); + release_mem_region (rinfo->fb_base_phys, + pci_resource_len(pdev, 0)); + + kfree (rinfo); } -#endif - -static void radeon_engine_init (struct radeonfb_info *rinfo) +static int radeon_engine_init (struct radeonfb_info *rinfo) { u32 temp; - + /* disable 3D engine */ OUTREG(RB3D_CNTL, 0); - radeon_engine_reset (); + radeon_engine_reset(rinfo); + + if (rinfo->arch pitch = ((rinfo->xres * (rinfo->bpp / 8) + 0x3f)) >> 6; + /* We re-read MC_FB_LOCATION from card as it can have been + * modified by XFree drivers (ouch !) + */ + rinfo->fb_local_base = INREG(MC_FB_LOCATION) pitch pitch fb_local_base >> 10)); + OUTREG(DST_PITCH_OFFSET, (rinfo->pitch fb_local_base >> 10)); + OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch fb_local_base >> 10)); - radeon_fifo_wait (1); + radeon_fifo_wait(rinfo, 1); +#if defined(__BIG_ENDIAN) + OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN); +#else OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN); +#endif - radeon_fifo_wait (1); + radeon_fifo_wait(rinfo, 1); OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX | DEFAULT_SC_BOTTOM_MAX)); temp = radeon_get_dstbpp(rinfo->depth); rinfo->dp_gui_master_cntl = ((temp dp_gui_master_cntl | GMC_BRUSH_SOLID_COLOR | GMC_SRC_DATATYPE_COLOR)); - radeon_fifo_wait (7); + radeon_fifo_wait(rinfo, 7); /* clear line drawing regs */ OUTREG(DST_LINE_START, 0); @@ -1595,7 +1957,9 @@ /* default write mask */ OUTREG(DP_WRITE_MSK, 0xffffffff); - radeon_engine_idle (); + radeon_engine_idle(rinfo); + + return 0; } @@ -1635,12 +1999,6 @@ disp = &rinfo->disp; disp->var = radeonfb_default_var; -#if defined(__powerpc__) - if (rinfo->dviDisp_type == MT_LCD) { - if (mac_vmode_to_var(VMODE_1152_768_60, CMODE_8, &disp->var)) - disp->var = radeonfb_default_var; - } -#endif rinfo->depth = var_to_depth(&disp->var); rinfo->bpp = disp->var. ...

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• Notify me of updates to Sleep Mask.

• Mask Frame System.
• Replacement mask frame for ResMed Ultra Mirage .
• Ultra Mirage Mask Cushion.
• Mask Frame.
• Replacement mask frame system for ResMed Ultra Mirage Mask .
• Replacement forehead support arm for ResMed Ultra Mirage Mask.
• Replacement forehead pads for ResMed Ultra Mirage Mask .
• Replacement cushion clip for ResMed Ultra Mirage Mask .
• Replacement headgear release clip for ResMed Ultra Mirage Mask.
• Replacement quick release swivel for ResMed Ultra Mirage mask.
• Replacement tubing for Mirage Mask.
• Mask Frame.
• Replacement mask frame for Mirage Mask.
• Replacement cushion for Mirage Mask.
• Replacement cushion for Mirage Mask.
• Replacement cushion for Mirage Mask.

• It is a machine that delivers air into your airways at a specific pressure set during a titration sleep study. ... The air is delivered through a mask, nasal interface or oral interface. For more information on masks visit the mask page. ...
• Today's CPAPs are quiet and small and there are many mask types available to suit each individual (none of them require glue!). ...
• Adjusting to CPAP can be difficult in the beginning for some, but most people after persevering for a while will find that they get so used to it that they can no longer sleep without it. ...
• Mask Recomendations .
• If you are diagnosed with sleep apnea. ... Untreated sleep apnea is now believed to be THE major cause of heart attack and stroke. The reason for this is that apnea means you stop breathing frequently when you sleep. ...
• as to wearing a CPAP mask, there are several things I want to mention. ...
• IF YOU'RE FEELING CLAUSTROPHOBIC or just generally uncomfortable sleeping with something on your face, sit with the mask on (not connected to the machine) for a while each day while you're doing some daily activity, like watching TV or reading a book, this gets you used to having something there and makes it easier then to sleep with it on.
• GET THE RIGHT MASK. ... The most common type is a nasal mask which fits over your nose kind of like oxygen masks in hospitals. ... The only report I have personally heard so far was in relation to the Fisher & Paykel Oracle mask. ...
• Ultra Mirage Mask.
• FISHER & PAYKEL ACLAIM (I have this one myself) mask which is particularly good for a number of reasons. ...

• Sleep Apnea .
• The use of nasal continuous positive airway pressure to treat obstructive sleep apnoea .
• Aim: To review 66 children with obstructive sleep apnoea (OSA) for whom a trial of nasal continuous positive airway pressure (nCPAP) was proposed. ...
• Methods: Baseline sleep studies were performed to assess OSA severity; a trial of nCPAP was performed where moderate to severe OSA, not relieved by adenotonsillectomy, was found. The nCPAP trial was considered either technically successful (ST), if the child accepted the mask for sufficient time to determine nCPAP efficacy, or a technical failure (FT) if otherwise. Patients with an initial FT were offered a period of home acclimatisation to familiarise them with wearing the mask during sleep. ...
• Keywords: obstructive sleep apnoea; nasal continuous positive airway pressure.
• Abbreviations: AS, active sleep; CPAP, continuous positive airway pressure; ECG, electrocardiogram; FT, failed treatment; nCPAP, nasal continuous positive airway pressure; OSA, obstructive sleep apnoea; QS, quiet sleep; ST, successful treatment.
• Nasal continuous positive airway pressure (nCPAP) for the treatment of obstructive sleep apnoea syndrome (OSA) was first described in 1981,1 and is now widely accepted as the first line therapy in adult patients. 2 CPAP acts as a pneumatic splint to the upper airway, serving to maintain airway patency, preventing the airway collapse associated with obstructive sleep apnoea. ... Follow up nCPAP assessments are recommended every 6–12 months, as mask size and effective nCPAP pressure are likely to change with growth. ...
• Figure 1 An infant undergoing a sleep study with nasal CPAP. The CPAP mask consists a rigid plastic frame with a soft silicone nasal cushion. The mask is held in place over the nose by a set of headgear with a three-point fixing to the mask frame using adjustable Velcro straps. ... Mask pressure is monitored during the CPAP trial via the narrow manometer tubing connected to the CPAP mask. ...
• 3,6–10 There are also a number of large studies referring specifically to the use of nCPAP to treat infantile sleep apnoea. ...

•   Magnetic Sleep-Mask -FM1 #4.
• The Sleep Mask is an all north pole magnetic face mask. ... Enjoy the benefits of magnetic therapy while you sleep. ...

• Sinus Mask.
• Health Solution Sleep Travel Kit.
• Travel and get better sleep with relaxation cd, music cd, sleep mask, aromatherapy and guide.
• Health Solution Sleep Kit.
• Better sleep with aromatherapy, a resistance cord device, video and sleep pea pillow.

• Sleep / Eye Mask.
• Insomnia / Jet Lag / Eye Mask Products.
• *Proven effectiveness at quieting and calming the central nervous system promoting a deep restful sleep! .
• And over time, not getting a restful nights sleep can lead to serious health and performance difficulties in many areas of ones life. ...
• This may explain its ability to help promote sleep and relaxation.
• Valerian extract provides safe, natural support to calm the central nervous system and encourage restful, refreshing sleep. ... ) improves sleep quality in man. ...
• *Supports the body's natural sleep cycle;.
• Air flight crews and travelers report significantly less Jet Lag and sleep disturbances due to Melatonin's ability to reset the body's timeclock.
• Melatonin is a hormone produced by the pineal gland, the organ which regulates the body's wake/sleep/wake cycle. ...
• sleep in middle-aged subjects. ...
• MindFold - Relaxation / Sleep Mask .
• MindFold is a sleep and travel mask impervious to light, including direct.
• sunlight! TOTAL darkness even with your eyes open! Uses: Sleep or relax while traveling .
• MindFold Relaxation Mask The MindFold Relaxation Mask is a flexible black plastic face plate backed with a high-density soft foam padding. The foam padding has cutouts that allow you to experience total darkness even with your eyes open! Our adjustable Velcro® head strap allows you to fit the MindFold mask snuggly to your face. No more loose or sagging mask problems! Comes with a FREE set of foam earplugs. ...

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